Integrated circuit (IC) design tools are designed for synchronous designs, and therefore, asynchronous designs must be constrained in IC design tools using synchronous constructs. As a result, the asynchronous design cycle using traditional design methodologies is typically longer than the synchronous design cycle.
Digital logic designs are composed of a plurality of pipeline stages that are clocked synchronously. Many digital logic designs only require a small percentage of pipeline stages to be clocked as the logic in these stages process information. However, current design methodologies using current design tools produce designs that clock more pipeline stages (for example flip-flops) in a logic design than necessary. Accordingly, there exists a need for solutions which improve over the state of the art.
This background information is intended to provide information that may be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.